The present invention relates to a semiconductor memory device and a refresh method for the semiconductor memory device.
In recent years, demands for lower power consumption of semiconductor memory devices, such as DRAMs (dynamic random access memory), are increasing. In particular, a strong desire exists for reducing current consumption in self-refresh operation, which is a data storing operation automatically executed to ensure data is maintained in a memory cell during standby.
FIG. 8 is a schematic block diagram of a semiconductor memory device (DRAM) describing a conventional self-refresh operation.
The semiconductor memory device 81 includes a memory cell array 82, an address buffer 83, an internal address counter 84, a predecoder 85, a block selection circuit 86, block con-rollers 87a to 87d, word line selectors 88a to 88d, and word decoders 89a to 89d. 
The memory cell array 82 is divided into a plurality of (e.g., four in the figure) cell blocks BLK0 to BLK3, each of which includes a plurality of memory cells as one unit. The block controllers 87a to 87d, the word line selectors 88a to 88d, and the word decoders 89a to 89d are arranged in correspondence with the cell blocks BLK0 to BLK3, respectively.
The internal address counter 84 provides an internal address signal IADD during refresh. During normal operation, the internal address counter 84 receives an externally provided address signal ADD via the address buffer 83, and provides an internal address signal IADD.
The block selection circuit 86 generates a selection signal φi (i=0 to 3, the same applies hereinafter) for selecting a cell block to be subjected to self-refresh, based on the address signal IADD.
The block controllers 87a to 87d generate control signals BLKENi and WLENi for selecting the word line selectors 88a to 88d and the word decoders 89a to 89d corresponding to the cell blocks BLK0 to BLK3, based on the selection signal φi.
The word line selectors 88a to 88d are activated based on the control signal BLKENi, and a predecode signal PREi output from the predecoder 85, and generate a drive signal WLDRVi for driving word lines of the corresponding cell blocks BLK0 to BLK3.
The word decoders 89a to 89d are activated based on the control signal WLENi, and the predecode signal PREi output from the predecoder 85, and drive word lines of the corresponding cell blocks BLK0 to BLK3, based on the drive signal WLDRVi provided from the word line selectors 88a to 88d. 
Bit lines of the cell blocks BLK0 to BLK3 are driven by a bit line precharge circuit 91 and a sense amplifier 92 (refer to FIG. 9), based on the selection signal φi output from the block selection circuit 86.
With the structure described above, when, for example, the cell block BLK0 is selected, only the memory cells included in the cell block BLK0 are refreshed.
The current consumed in a refresh operation (refresh current) includes a DC (direct current) component that is consumed steadily, and an AC (alternating current) component that is consumed in the refresh operation for memory cells. The DC component includes a tailing current (also referred to as an off leak current) generated due to the subthreshold of a peripheral circuit, and current consumed due to a physical deficiency. The AC component includes a charging and discharging current used in the refresh operation for memory cells.
One important way to reduce refresh current is by reducing the DC component and the AC component.
As one conventional factor in increasing refresh current, a process deficiency may cause a word line and a bit line to be short-circuited. If this happens, a leakage current (a deficient current) steadily flows from the bit line to the word line via the deficient portion (short-circuited portion).
FIG. 9 is a circuit diagram describing such a deficient current.
As shown in FIG. 9, a word line WL and a bit line BL are short-circuited (as indicated by a dashed line in the figure). The sense amplifier 92 connected to the bit line BL is provided with a precharge signal PR from the bit line precharge circuit 91. The bit line BL is precharged to have a predetermined potential (e.g., ½ VDD) when the corresponding cell block is not selected. The power supply VDD is the operating power supply for each circuit. The word decoder 89a (89b, to 89d) connects the word line WL to a low potential power supply VSS (e.g., ground) when the corresponding cell block is not selected. As indicated by the arrow in the figure, a steady leakage current flows from the bit line BL to the word line WL.
Such a deficient portion (the word line WL, the bit line BL, etc.) caused by a process deficiency may be replaced by a redundant circuit, which is arranged in advance. However, the replacement does not eliminate the physical electric deficiency characteristic of the deficient portion. Thus, current flowing through the deficient position becomes a steady consumption current, and increases the DC component described above. Such a deficient portion is randomly generated. Further, the number of such deficient portions tends to increase as the scale of integration of memory cells increases toward finer processes. As a result, power consumption during self-refresh increases by the amount of such a steady deficient current. This is a major obstacle to realizing low power consumption.
To reduce such deficient current, for example, Japanese Laid-Open Patent Publication No. 2000-268571 proposes a first method described below. According to the first method, when a word line and a bit line are short-circuited during self-refresh, a precharge level for the bit line is set at a level corresponding to a floating state (e.g., ground level). In this way, the first method reduces the deficient current.
However, the first method has a problem at the time of switching from self-refresh operation (standby state) to a read/write operation (normal state). At the time of such switching, a long time is required to recover the level of the bit line, which is substantially at ground level, to a normal level (sense level). Thus the first method fails to realize high-speed recovery from the standby state to the normal state.
In the first method, to prevent deficient current from being generated, each bit line connected to a memory cell that is yet to be refreshed is first controlled to have a potential in a floating state. Then, when the memory cell is to be refreshed, each bit line is controlled back to have a predetermined potential (½ VDD). A charging and discharging operation executed along with such control increases the AC component. Thus, the first method may rather increase power consumption.
Further, the first method requires a test unit, which includes a fuse and an insulation gate, to be arranged in advance for all bit lines, to enable a deficient portion to be specified. The first method also requires a control unit for controlling each bit line based on deficiency information obtained by the test unit. Thus, the first method has the problem of an extremely large chip area. The first method further requires a testing process for specifying a deficient portion using the test unit described above, and a deficiency information storing process for storing deficiency information obtained by the testing process (disconnecting a fuse, turning off an insulation gate, etc.). Thus, the first method also has the problem of a high testing cost. One prior art technique relating to another conventional structure having these problems is disclosed, for example, in U.S. Pat. No. 6,366,509.
Further, for example, Japanese Laid-Open Patent Publication No. 8-203268 proposes a second method described below. According to the second method, all bit lines are controlled to be in a floating state when the corresponding memory cells are not accessed (i.e., when the corresponding cell block is not selected) regardless of whether the bit lines have a deficiency. In this way, the second method reduces deficient current.
However, the second method is unrealistic. In particular, a DRAM executes such an operation that transmits, as memory cell information, an extremely small amount of charge, which is accumulated in a capacitor having an extremely small area, to a bit line, and differentially amplifies a subtle amplitude of the bit line. Thus, if all the bit lines are controlled to be in a floating state, the potential of all the bit lines may become unstable. Then, a coupling noise may be generated in a bit line (non-deficient bit line) adjacent to a bit line having a deficient portion, and may cause the non-deficient bit line to have an unintended noise potential. As a result, a memory cell connected to the adjacent bit line may be turned on, and the storage contents of the memory cell may be changed. In this way, the second method may cause information destruction.
Further, for example, Japanese Laid-Open Patent Publication No. 8-102529 proposes a third method described below. The third method relates to a double word-line structure in which each word line is composed of a main word line and a sub word line. The double word-line structure intends to realize higher speed and lower power consumption of a large-capacity DRAM. According to the third method, each main word line includes a fuse, and a fuse in a line having a deficient portion is disconnected, to control its sub word line to be in a floating state. In this way, the third method reduces deficient current.
However, with each main word line including a fuse, the third method also has, like the first method, the problems of a large chip area and high testing cost.
Further, when a word line having a deficient portion is controlled to be in a floating state, a word line (non-deficient word line) adjacent to the deficient word line may have a coupling noise. Like the second method, the third method may also cause destruction of memory cell information. Further, with the third method, the deficient word line is controlled to be in a floating state. Thus, a bit line connected to an effective memory cell may have a coupling noise. This may cause erroneous reading of the memory cell.